LMX2532LQX1065/NOPB【PDF 2/18 页】PLL FREQUENCY SYNTHESIZER, 19.68 MHz, QC

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Programming Description

CONTROL REGISTER CONTENT MAP

The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming Data is loaded into the shift

register from MSB to LSB. The Data is shifted at the rising edge of the Clock signal. When the Latch Enable signal transitions from

LOW to HIGH, the data stored in the shift register is transferred to the proper register depending on the address bit settings. The

selection of the particular register is determined by the control bits indicated in boldface text.

At initial start-up, the MICROWIRE loading requires 4 default words (registers R3, loaded first, to R0, loaded last). After the device

has been initially programmed, the RF VCO frequency can be changed using a single register (R0). If an IF frequency other than

the default value for the device is desired the SPI_DEF bit should be set to 0, the desired values for IF_A, IF_B, and IF_R entered

and words R6 to R0 should be sent.

The control register content map describes how the bits within each control register are allocated to the specific control functions.

Complete Register Map

Register

MSB

SHIFT REGISTER BIT LOCATION

LSB

18 17 16 15 14 13 12

10 98765

1 0

(Default)

SPI_

DEF

RF_

SEL

RF_

UR_

CRL

RF_B

[3:0]

RF_A

[2:0]

RF_FN

[10:0]

(Default)

IF_

FREQ

[1:0]

OSC_

FREQ

000000

SPUR_

RDT

[1:0]

0101OB_

CRL

[1:0]

RF_

IF_

(Default)

IF_

CUR[1:0]

0011101

10100

(Default)

BW_

DUR

[1:0]

BW_

CRL

[1:0]

BW_

1011110

00110

VCO_

CUR

[1:0]

01 1

IF_A

[3:0]

IF_B

[8:0]

1 1

00010

IF_R

[8:0]

1 1

0000000

0000 011

1 1

NOTE: Bold numbers represent the address bits.

LMX2522/LMX2532

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